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JCR. 2020; 7(4): 1410-1416

Design of Low-power Multiplier using Spurious Power Suppression Technique (SPST)

Dr. A. Lakshmi, M.E., Dr. Kyung Tae Kim., M. Tanmayi, K. Pavani.

The working motto of our project is to design a low power multiplier with the needless power consumption technique. When portion of information doesn’t have an effect on ultimate computing result, dominant circuits of the SPST (Spurious Power Suppression Technique) latches this portion to neglect needless data-transition taking place in arithmetic devices, in order that the needless spurious alerts of the arithmetic units are cleared out. To clear out the vain power, there exists two strategies, i.e. through registers and through AND gates. Here, we propose a multiplier of low- power adopting new SPST approach. This kind of multiplier is designed through adopting the SPST on a Modified-Booth Encoder that is controlled by means of the detection unit with the usage of AND gate. Modified-Booth Algorithm is employed in this paper that reduces the partial product to n/2. The SPST adder neglects undesirable addition, hence minimizes the switching power-dissipation. Modelsim software has been used here for the logic verification of the multipliers.

Key words: Booth encoder, SPST, Low-power.

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