Stability of static random access memory (SRAM) cells has become a growing concern in the nanometer regime. In order to address this issue, this paper proposes a read-decoupled 10 transistor (10T) SRAM cell. The decoupled-read feature of the proposed 10T SRAM cell protects it from the read-disturbance problem, thereby achieving enhanced read stability. Additionally, the bit interleaving capability of the cell provides immunity to soft errors. The simulation is performed on TSPICE software using a 32 nm CMOS predictive technology model. The obtained results reveal that the read static noise margin - at 400 mV - of the proposed design is 4.77x and 1.38x larger compared to that of a 6T cell and the Schmitt-trigger based 10T cell, respectively. Moreover, the write power consumption in the proposed design is found to be 1.86x lesser than that of a 6T cell. Furthermore, the proposed circuit exhibits 3.47x lesser static power consumption compared to a 6T cell.
Key words: Bit interleaving; Read static noise margin; Leakage power; SRAM; Write static noise margin; CMOS.
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