A low power energy efficient Dual channel multiplier is being evaluated here with FPGA hardware implementation to diminish the complexity of multiplier units in most of the DSPs for floating point operations. The novel DCM architecture is designed using the distributed architecture in RTL code, and the evaluation of application unit is design for validating the circuit flexibility. Design of an adaptive synthesizer is being designed using the implemented dual channel multiplier. The distributed functioning of DCM clearly depicts the reduced number of steps and logical elements. The proposed framework implies the XILINX ISE based frequency synthesizer design uses Low power clock gated techniques to reduce the power consumption naturally. XILINX SPARTAN XC3S250E device is used for implementation. The proposed architecture is also compared with Vedic multiplier-based synthesizer architecture in terms of power and area utilization.
Key words: Dual channel multiplier, synthesizer design, distributed arithmetic, low power design etc.
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