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Research Article

JCR. 2020; 7(2): 977-981


IMPLEMENTATION OF HIGH-PERFORMANCE WALLACE TREE MULTIPLIER USING COMPRESSORS

Usha Rani.Nelakuditi, Anil Kumar kurra, Haritha.Dasari.

Abstract
Multiplication is widely used arithmetic operation in high-speed computation applications such as DSP, Communications, Signal and Image Processing. In many Cases System speed performance is decided by the multiplier. Out of available multipliers Wallace tree multiplier is quite faster one. Speed of a conventional Wallace tree multiplier can be further increased by using compressors. Higher order compressors gives better performance than basic 3:2 compressor by reducing number of stages. This work aims at designing and implementing a 32-bit high performance Wallace tree multiplier by using compression technique and implemented in Questa sim Tool. Code is generated using verilog and synthesis is performed by using Leonardo spectrum 130nm technology.

Key words: DSP Processors, Conventional Wallace Tree Multiplier, Leonardo Spectrum



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