High speed architectures for finding the first two max/min values are of paramount importance in several applications, including iterative decoders and for proposed the adder and Low density parity check code (LDPC) has been implemented. The min-sum processing that it produces only two different output magnitude values irrespective of the number of incoming bit-to check messages. The new microarchitecture structures would employ the minimum number of comparators by exploiting the concept of survivor in the search. These result in reduced number of comparisons and consequently reduced energy use. Multipliers are complex units and play an important role in deciding the overall area, speed and power consumption of digital designs. The main feature of proposed algorithm is the use of the optimization factor. Also, the Optimization factor is not multiplied in posterior information which reduces complexity of the algorithm. By using the multiplier to reduce the parameters like latency, complexity and power consumption.
Low density parity check code (LDPC),microarchitecture structures, optimization factor