Abstract

Several systems have been developed to deal with ECG noises. However, the majority lack real-time processing and are high hardware and power consumers. The high computational complexity of the objective algorithms is behind these drawbacks. The adaptive dual threshold filter (ADTF) is a recent method that has shown its denoising efficiency of ECG signals. This paper presents a low hardware and power ADTF based embedded architecture that allows high-quality ECG signal denoising in real-time and at low processing frequencies.

The proposed method is a pipelined hardware FPGA-based architecture. Thanks to the ADTF’s low complexity, a non-structural design approach is adopted, and significant resource needs are reduced. Additionally, the binary representation of the input data is modified so that unsigned data is handled within few representative bits. Consequently, fixed-point is effectively applied. Further, needed clock cycles for the maximum/minimum computing are reduced using parallel multiplexers and registers. Therefore, 1.44 kHz is used, which is only four times the ECG data acquisition frequency.

The denoising quality is assessed using the PRD and SNR improvement. The power, resource, and time consumption benchmarks evaluate the architectural performance. Significant outcomes are given by the proposed architecture compared to existing systems.

The ADTF represents an efficient solution against ECG noise thanks to its low complexity. The corresponding proposed architecture provides efficient results that outperform those related to the previous ADTF architectures and other works. Furthermore, the proposed architecture represents a suitable low hardware and power solution for real-time ECG monitoring systems.

Key words: ECG; Denoising; Real-time; FPGA; Embedded; Hardware; Pipeline; VHDL; Low-frequency; Low-power.