Abstract

Power dissipation stands as a crucial challenge in VLSI design, especially for high-speed counters used in frequency synthesizers, PLLs, and digital converters. Conventional binary counters suffer from large fan-out and propagation delays, while traditional LFSR counters operate with only (2^m – 1) states, requiring additional circuitry for full counting sequences. This work proposes a novel LFSR counter with a state extension technique that achieves 2^m states without degrading the counting rate. The architecture combines a low-order LFSR sub-counter and a high-order synchronous binary counter, optimized with clock gating to reduce unnecessary switching activity. Implemented using Verilog HDL in Xilinx ISE/Vivado, the proposed design demonstrates significant improvements: power reduced from 249 mW to 114 mW (54% savings) while maintaining constant delay performance. Compared to conventional binary and LFSR counters, the design achieves superior trade-offs in power, speed, and area, making it highly suitable for advanced high-speed VLSI applications.

Key words: Arithmetic and Logic units; Clock gating, Combinational Logic; High speed Arithmetic; High Speed Counter; LFSR State Extension; Low Power Techniques; Sequential circuits.