nowadays, the modern microelectronics digital communication systems are using low power and efficient design for wide variety of applications in real world. Recent researchers focusing on amplifier circuits for increasing applications with novel designs; conventional method uses FinFET CMOS design, and other reconfigurable designs, which consumes much power on designing and to overcome the design complexity of existing work, the proposed optimal power reduction strategy is employed on the ADC lock-in amplifier. Here the two stage lock-in amplifier is constructed with gated clocking of DFF switching strategy to reduce the power consumption and to obtain better results than previous works. Virtext FPGA model of amplifier is designed with Xilinx ISE 14.2 tool. The design of lock-in Amplifier has both sensing stage and latch stage with better sampling periods of edge triggering state, which improves the performance. High speed FPGA with mixed signal processing application is capable for this design. Experimental results analyzed with the power, area and delay as major concern and switching state with clocking model determines the high speed design. By comparing with the previous work, the proposed work is designed to achieve better results.
Key words: ADC; FPGA Virtex and gated clock; Lock-in Amplifier; Power reduction approach.
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