Increasing demand of portable devices creating larger scope in the field of Low power device design. VLSI designing of the efficient circuits is aiming towards the devices consuming less power and produces less delay with capability to operate in wider range of frequencies. This research paper proposes the modified Single Edge Triggered (SET) D-flip flop design for the low power applications. The earlier proposed design is tested for various substrate bias techniques in sub threshold region to opt for better design.
Key words: SET DFF, low power, high speed